1. Field of the Invention
The invention relates in general to a chip structure and a process for forming the same. More particularly, the invention relates to the process with simplified steps and its corresponding chip structure.
2. Description of the Related Art
The way to improve the performance of a semiconductor device is usually to reduce the geometric dimensions of the Integrated Circuits. It results in the reduction in the cost per die and the improvement of performance. A metal connection between Integrated Circuits and other circuits or between Integrated Circuits and system components is becoming relatively important and has an increasingly negative impact on the circuit performance, while Integrated Circuits are more miniaturized.
The increase of the parasitic capacitance and resistance induced by the metal interconnections increase degrades the chip performance significantly. Of most concerns are the voltage drop along power and ground buses and the RC delay of critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher parasitic capacitance induced by these wider metal lines. To solve this problem, a metal of low resistance, such as copper, is introduced as the conducting wires and a dielectric material with low dielectric constant (k) is used between the signal lines. According to the historical point of view of the metallization structure for IC, since 60s the sputtered aluminum dominated as the material for connecting metal. An aluminum thin-film layer is formed to cover the whole chip by using a sputtering process and then patterned by a photolithography process and a dry or wet etching process. Due to the cost and the thin-film stress formed by a sputtering process, the technique for forming an aluminum circuit with a thickness of more than 2 microns is very difficult and expensive.
In about 1995, a damascene copper became another material for connecting metal in IC. According to the damascene copper process, after patterning an insulating layer, a copper layer is formed by an electroplating process inside the opening in the insulating layer and on the insulating layer. Then, the copper layer outside the opening in the insulating layer is removed by using a Chemical Mechanical Polishing/Planarization (CMP). As a result, the copper trace can be formed inside the opening in the insulating layer.
However, the thick metal layer electroplated onto the whole chip has a relatively large inner stress and the thickness of the damascene copper layer depends on the thickness of the insulating layer made of, for example, a Chemical-Vapor-Deposition (CVD) oxide. Because of the concern about the inner stress and the cost, the damascene copper process can not form a thicker copper trace. In other words, it is difficult in aspect of technology and expensive in cost to form a copper wire that is thicker than 2 microns.
Nakanishi (U.S. Pat. No. 5,212,403) discloses a method of forming wiring connections both inside and outside in a wiring substrate, especially a logic design varying with the length of the wiring connections.
Gehman, Jr. et al. (U.S. Pat. No. 5,501,006) shows a structure with an insulating layer between integrated circuits (IC) and a wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of a circuit board.
Jacobs (U.S. Pat. No. 5,055,907) discloses an integrated semiconductor structure allowing manufacturers to integrate circuitry beyond a chip by forming multiple thin-film wiring layers over a support substrate and over the chip.
Volfson et al. (U.S. Pat. No. 5,106,461) teaches a multi-layer interconnect structure with alternating an insulating layers of polyimide, formed over a chip, and with a TAB structure.
Wenzel et al. (U.S. Pat. No. 5,635,767) teaches a method for reducing RC delay by a PBGA with multiple separate metal layers.
Fulcher (U.S. Pat. No. 5,686,764) shows a flip-chip substrate that reduces RC delay by separating the power traces from I/O traces.
In the book of “Silicon Processing for the VLSI Era” (Vol. 2, pp. 214-217, Lattice Press, Sunset Beach, Calif. c. 1990), written by Stanley Wolf, it is discussed that polyimide is used as an insulating layer between metals in 80s. However, due to some disadvantages in polyimide, polyimide has not been used for that purpose.